The present invention relates to a semiconductor structure applicable to semiconductor devices, such as MOSFET""s (insulated gate field effect transistors), IGBT""s (insulated gate bipolar transistors), bipolar transistors and diodes. More specifically, the present invention relates to a semiconductor structure, which facilitates realizing a high breakdown voltage and a high current capacity in a power semiconductor device.
Semiconductor devices may be classified into lateral devices, wherein the main electrodes thereof are on one major surface, and vertical devices that distribute the main electrodes thereof on two major surfaces facing opposite to each other. In the vertical semiconductor device, a drift current flows in the thickness direction of the semiconductor chip (vertically) in the ON-state of the semiconductor device and depletion layers expand also in the thickness direction of the semiconductor chip (vertically) in the OFF-state of the semiconductor device.
FIG. 14 is a cross sectional view of a conventional planar-type n-channel vertical MOSFET (vertical double-diffused MOSFET). Referring now to FIG. 14, the MOSFET includes an n+-type layer 11 with low electrical resistance, a drain electrode 18 in electrical contact with n+-type layer 11, an n┘-type drain drift layer 12 with high electrical resistance on n+-type layer 11, p-type base regions (p-type well regions) 13 formed selectively in the surface portion of n┘-type drain drift layer 12, n+-type source regions 14 and a heavily doped p+-type contact region 19 formed selectively in the surface portion of p-type base region 13, a polycrystalline silicon gate electrode layer 16 above the extended portion of p-type base region 13 extended between n+-type source region 14 and n┘-type drain drift layer 12 with a gate insulation film 15 interposed therebetween, and a source electrodes 17 in contact commonly with n+-type source regions 14 and p+-type contact regions 19.
In the vertical MOSFET as described above, highly resistive n┘-type drain drift layer 12 provides a vertical drift current path in the ON-state thereof. Since highly resistive n┘-type drain drift layer 12 is biased at a reverse bias potential in the OFF-state of the MOSFET, n┘-type drain drift layer 12, depleted by the depletion layers expanding from the pn-junctions between p-type base regions 13 and n┘-type drain drift layer 12, provides the MOSFET with a high breakdown voltage. Thinning highly resistive n┘-type drain drift layer 12, (that is, shortening the drift current path), facilitates reducing the on-resistance (the resistance between the drain and the source), since the drift resistance in the ON-state of the semiconductor device is reduced. However, the thinning, highly resistive n┘-type drain drift layer 12 narrows the width between the drain and the base, in that depletion layers expand from the pn-junctions between p-type base regions 13 and n┘-type drain drift layer 12. Due to the narrow expansion width of the depletion layers, the depletion electric field strength soon reaches the maximum (critical) electric field strength for silicon. Therefore, breakdown is caused at a voltage between the drain and the source lower than the designed breakdown voltage. A high breakdown voltage is obtained by thickening n┘-type drain drift layer 12. However, a thick n┘-type drain drift layer 12 with high resistance inevitably causes high on-resistance, and that further increases loss. In other words, there exists a tradeoff relationship between the on-resistance (current capacity) and the breakdown voltage. The tradeoff relationship between the on-resistance and the breakdown voltage also exists in other semiconductor devices such as IGBT""s, bipolar transistors and diodes, which have a drift layer.
European Patent 0 053 854, U.S. Pat. No. 5,216,275, U.S. Pat. No. 5,438,215, Japanese Unexamined Laid Open Patent Application H09-266311 and Japanese Unexamined Laid Open Patent Application H10-223896 disclose semiconductor devices, which facilitate reducing the tradeoff relation between the on-resistance and the breakdown voltage. The vertical drift sections of the semiconductor devices are formed of an alternating conductivity type layer including heavily doped n-type regions and heavily doped p-type regions alternately arranged.
FIG. 15 is a cross sectional view of a vertical MOSFET disclosed in U.S. Pat. No. 5,216,275. Referring now to FIG. 15, the vertical MOSFET disclosed in the above identified U.S. patent includes a drain drift layer 22, that is not a uniform impurity diffusion layer of one conductivity type but an alternating conductivity type layer formed of n-type drift current path regions 22a and p-type partition regions 22b arranged alternately. The n-type drift current path regions 22a and p-type partition regions 22b are shaped with respective layers extending vertically. Since depletion layers expand laterally from the vertically extending pn-junctions between n-type drift current path regions 22a and p-type partition regions 22b in the OFF-state of the MOSFET, the entire drain drift layer 22 is depleted. In other words, a thick depletion layer is obtained in the OFF-state of the MOSFET. Therefore, the vertical MOSFET shown in FIG. 15 facilitates obtaining a high breakdown voltage even when the impurity concentrations in n-type drift current path regions 22a and p-type partition regions 22b are high. Hereinafter, the semiconductor device including an alternating conductivity type layer, that provides a current path in the ON-state of the device and is depleted in the OFF-state of the device, will be referred to as the xe2x80x9csuper-junction semiconductor devicexe2x80x9d.
Alternating-conductivity-type drain drift layer 22 beneath the active regionxe2x80x94including p-type base regions 13xe2x80x94facilitates realizing a higher breakdown voltage. However, alternating-conductivity-type drain drift layer 22 poses another problem on the super-junction semiconductor device described above. During the transition from the ON-state to the OFF-state, a strong electric field tends to remain beneath gate insulation film 15 due to the well curvature of p-type base regions 13. In the super-junction semiconductor device, depletion layers expand very quickly from the pn-junctions between p-type base regions 13 and drift current path regions 22a and from the pn-junctions between drift current path regions 22a and p-type partition regions 22b into drift current path regions 22a, causing an instantaneous pinching effect. The instantaneous pinching effect accelerates carrier ejection from drift current path regions 22a and hot carrier injection into gate insulation films 15. Due to the accelerated hot carrier injection, the deterioration of gate insulation films 15 lowers the threshold voltage, which further impairs the characteristics and the reliability of the active region of the device.
In the conventional semiconductor device which does not include any alternating-conductivity-type drain drift layer, and/or depletion layers expanding from p-type base regions 13 toward the layer with low electrical resistance 11, separate carriers from gate insulation film 15. Since depletion layers expand all at once in the super-junction semiconductor device, the accumulated carriers have no place to escape. The ejected carriers encounter the strong electric field beneath gate insulation film 15, causing hot carriers, which will be injected into gate insulation film 15. Although depletion layers expand quickly in the vicinity of p-type base regions 13 doped lightly, lightly doped p-type base regions 13 directly affect the threshold voltage.
The problems described above occur not only in the vertical double-diffused MOSFET""s, but also in other vertical super-junction semiconductor devices such as vertical IGBT""s, vertical bipolar transistors and vertical diodes, which include an insulation film on the active region. In view of the foregoing, it would be desirable to provide a super-junction semiconductor device that facilitates in preventing hot carriers from being injected into the insulation film so that the characteristics and the reliability of the active region thereof will not be impaired.
The present invention obviates the problems described above by intentionally disposing sacrifice regions outside the active region for making the electric field strengths in the sacrifice regions reach the maximum (critical) value in advance to the electric field strength in the portions beneath the gate insulation films so that strong electric fields may not be caused beneath the gate insulation films.
According to the present invention, there is provided a semiconductor device including: a semiconductor chip having a first major surface and a second major surface facing opposite to the first major surface; a first main electrode on the first major surface; a second main electrode on the second major surface; an active region in electrical contact with the first main electrode; a layer with low electrical resistance in electrical contact with the second main electrode; an alternating-conductivity-type layer between the active region and the layer with low electrical resistance; the alternating-conductivity-type layer including first semiconductor path regions of a first conductivity type and second semiconductor regions of a second conductivity type; the first semiconductor regions and the second semiconductor regions being arranged alternately; and the alternating-conductivity-type layer further including breakdown voltage limiter regions of the second conductivity type for making the electric field strength thereof reach the critical value prior to the electric field strength in the active region.
Since breakdown is caused in the breakdown voltage limiter regions, the electric fields thereof reach the critical value prior to the electric field beneath the first major surface, and a strong electric field is not caused beneath the first major surface. Also, hot carrier injection to the first major surface is prevented from causing. Therefore, the characteristics and the reliability of the active region in the super-junction semiconductor device according to the invention, which exhibit a high breakdown voltage and a high current capacity, are not impaired.
The breakdown voltage limiter regions may be of the first conductivity type and formed in the respective first semiconductor regions. However, the hot carriers caused at the location spaced apart from the first major surface by breakdown may hit the first major surface when the breakdown voltage limiter regions are in the respective first semiconductor regions. Therefore, it is preferable to form the breakdown voltage limiter regions in the respective second semiconductor regions. The breakdown voltage limiter region is formed preferably in any location in the partition region such as the location in the vicinity of the active region and the location spaced apart from the active region.
The performance of the breakdown voltage limiter region is defined by the impurity amount therein, which is a product of the width and also the impurity concentration of the breakdown voltage limiter region. Advantageously, the impurity amount in the breakdown voltage limiter region will be higher than the impurity amount in an adjacent first conductivity type region of the second semiconductor region.
Although the breakdown voltage is reduced when the width of the breakdown voltage limiter region is equal to the width of the first conductivity type region and the impurity concentration in the breakdown voltage limiter region is higher than the impurity concentration in the first conductivity type region, on-resistance increase is prevented from causing. Since the reduction of the breakdown voltage is not so large as the addition of the breakdown voltage obtained by employing the alternating-conductivity-type layer, the breakdown voltage of the super-junction semiconductor device according to the invention is still higher than the breakdown voltage of the conventional semiconductor device, which does not employ any alternating-conductivity-type layer. On-resistance increase is caused when the breakdown voltage limiter region is wider than the first conductivity type region and the impurity concentration in the breakdown voltage limiter region is equal to the impurity concentration in the first conductivity type region, since the first semiconductor regions are pinched. Since the increment of the on-resistance is not so large as the decrement of the on-resistance obtained by employing the alternating-conductivity-type layer, the on-resistance of the super-junction semiconductor device according to the invention is still lower than the on-resistance of the conventional semiconductor device which does not employ any alternating-conductivity-type drain drift layer. The on-resistance is slightly increased by setting the impurity concentration and the width of the breakdown voltage limiter region larger than the impurity concentration and the width of the first conductivity type region, respectively.
Advantageously, the planar pattern of the first semiconductor regions and the second semiconductor regions is a laminate formed of the stripes of the first semiconductor regions and the stripes of the partition regions alternately arranged.
Advantageously, the first semiconductor regions and the second semiconductor regions are shaped with respective columns arranged at the lattice points of a planar lattice.
Alternatively, the first semiconductor regions or the second semiconductor regions are shaped with walls forming a honeycomb.
Advantageously, the active region constitutes a double-diffused MOSFET structure, a diode junction stricture, a bipolar transistor structure and such a semiconductor structure.